This specification relates to polishing pads useful for polishing or planarizing semiconductor substrates. The production of semiconductors typically involves several chemical mechanical polishing (CMP) processes. In each CMP process, a polishing pad in combination with a polishing solution, such as an abrasive-containing polishing slurry or an abrasive-free reactive liquid, removes excess material in a manner that planarizes or maintains flatness for receipt of a subsequent layer. The stacking of these layers combines in a manner that forms an integrated circuit. The fabrication of these semiconductor devices continues to become more complex due to requirements for devices with higher operating speeds, lower leakage currents and reduced power consumption. In terms of device architecture, this translates to finer feature geometries and increased numbers of metallization levels. These increasingly stringent device design requirements are driving the adoption of smaller and smaller line spacing with a corresponding increase in pattern density. The devices' smaller scale and increased complexity have led to greater demands on CMP consumables, such as polishing pads and polishing solutions. In addition, as integrated circuits' feature sizes decrease, CMP-induced defectivity, such as, scratching becomes a greater issue. Furthermore, integrated circuits' decreasing film thickness requires improvements in defectivity while simultaneously providing acceptable topography to a wafer substrate; these topography requirements demand increasingly stringent planarity, line dishing and small feature array erosion polishing specifications.
Historically, cast polyurethane polishing pads have provided the mechanical integrity and chemical resistance for most polishing operations used to fabricate integrated circuits. For example, polyurethane polishing pads have sufficient tensile strength and elongation for resisting tearing; abrasion resistance for avoiding wear problems during polishing; and stability for resisting attack by strong acidic and strong caustic polishing solutions. The IC1000™ polishing pad supplied by Dow Electronic Materials represents the industry standard polyurethane polishing pad suitable for polishing multiple substrates, such as aluminum, barrier materials, dielectrics, copper, hard masks, low-k dielectric, tungsten and ultra low-k dielectrics (IC1000 is a trademark of Dow Electronic Materials or its affiliates.).
M. J. Kulp, in U.S. Pat. No. 7,169,030, discloses a family of polyurethane polishing pads having high tensile modulus. These polishing pads provide excellent planarization and defectivity for several combinations of polishing pads and polishing slurries. For example, these polishing pads can provide excellent polishing performance for ceria-containing polishing slurries, for polishing silicon oxide/silicon nitride applications, such as direct shallow trench isolation (STI) polishing applications. For purposes of this specification, silicon oxide refers to silicon oxide, silicon oxide compounds and doped silicon oxide formulations useful for forming dielectrics in semiconductor devices; and silicon nitride refers to silicon nitrides, silicon nitride compounds and doped silicon nitride formulations useful for semiconductor applications. Unfortunately, these pads do not have universal applicability for improving polishing performance with all polishing slurries for the multiple substrate layers contained in today's and future semiconductor wafers. Furthermore, as the cost of semiconductor devices decreases, there remains a need for further and further increases in polishing performance.
For patterned wafers, nonferrous metal polishing such as copper polishing remains an important demanding application for integrated circuit and memory applications. In the manufacture of semiconductors a copper layer often blankets the entire wafer. The polishing pad must provide excellent bulk copper removal, leaving a network of copper interconnects. There remains a demand for polishing pads with improved polishing performance for nonferrous substrates, such as copper polishing.
In addition, increasing a polishing pad's removal rate can increase throughput to decrease a semiconductor fabrication plant's equipment footprint and expenditure. Because of this demand for increasing performance, there remains a desire for a polishing pad to remove substrate layers with increased performance. For example, oxide dielectric removal rates are important for removing dielectrics during inter-layer dielectric (“ILD”) or inter-metallic dielectric (“IMD”) polishing. Specific types of dielectric oxides in use include the following: BPSG, TEOS formed from the decomposition of tetraethyloxysilicates, HDP (“high-density plasma”) and SACVD (“sub-atmospheric chemical vapor deposition”). There is an ongoing need for polishing pads that have increased removal rate in combination with acceptable defectivity performance and wafer uniformity. In particular, there is a desire for polishing pads suitable for ILD polishing with an accelerated oxide removal rate in combination with acceptable planarization and defectivity polishing performance.